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seiko epson corporation 1 pf761-04 e0c6s32 4-bit single chip microcomputer low voltage operation products l core cpu architecture l svd circuit/comparator l event counter n description the e0c6s32 is an advanced single-chip cmos 4-bit microcomputer consisting of the e0c6200a 4-bit core cpu. it also contains the rom, ram, lcd driver, event counter, svd circuit, stopwatch counter, and time base counter. with wide voltage range and low power consumption, the e0c6s32 provides an excellent solution for the low-power consumption systems with manganese dry cell. n features l cmos lsi 4-bit parallel processing l clock ..................................................... 32.768khz (typ.)/1mhz (typ.) (selectable by software) l instruction set ........................................ 100 instructions l instruction cycle time ............................ 153sec, 214sec or 366sec at 32khz (depending on instruction) 5sec, 7sec or 12sec at 1mhz (depending on instruction) l rom capacity ....................................... 2,048 12 bits l ram capacity ........................................ 144 4 bits l input port ............................................... 5 bits (pull-down resistors are available by mask option) l output port ............................................ 4 bits (general purpose) 2 bits (buzzer output): bz, bz 1 bit (lamp output) 1 bit (clock output) l i/o port .................................................. 8 bits l lcd driver ............................................. 38 segments 2, 3 or 4 commons (1/2, 1/3 or 1/4 duty is selectable by mask option) l built-in time base counter l built-in stopwatch counter l built-in watchdog timer l event counter ........................................ 8 lines l built-in amp .......................................... operational amp for mos input analog comparator l built-in svd ........................................... 1.2 0.1v/2.4 0.1v (supply voltage detector) l interrupts ............................................... external : input interrupt 2 lines internal : timer interrupt 1 line stopwatch interrupt 1 line l current consumption ............................ e0c6sl32/6sb32 halt mode (32khz) : 1.0a (typ.) e0c6s32 halt mode (32khz) : 1.2a (typ.) e0c6sa32 halt mode (32khz) : 1.5a (typ.) operating mode (1mhz) : 300a (typ.) l package ................................................ qfp5-80pin (plastic), qfp14-80pin (plastic) die form n line up model supply voltage 1.5v (0.9v to 1.8v) 3.0v (1.8v to 3.6v) 3.0v (2.2v to 3.6v) wide voltage (0.9v to 3.6v) e0c6sl32 e0c6s32 e0c6sa32 e0c6sb32 clock 32khz (crystal oscillation) 32khz (crystal oscillation) 32khz (crystal oscillation) & 1mhz (ceramic or cr oscillation) 32khz (crystal oscillation)
2 e0c6s32 n block diagram n pin configuration com0~3 v k00~03, k10 p00~03, p10~13 r00~03, r10~13 ampp ampm dd osc4 osc3 osc2 osc1 reset seg0~37 test v l1~3 ca, cb v s1 v ss power controller lcd driver ram 144 words x 4 bits rom 2,048 words x 12 bits osc system reset control event counter interrupt generator input port i/o port output port comparator timer stop watch core cpu e0c6200a svd qfp5-80pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 seg17 test seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 no. pin name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg36 seg37 ampp ampm k10 k03 k02 k01 k00 p03 p02 p01 p00 p13 p12 p11 p10 r03 r02 r01 no. pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 r00 r12 r11 r10 r13 v ss reset osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 n.c. cb ca com3 n.c. = no connection no. pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 com2 com1 com0 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 no. pin name 41 64 25 40 index 24 1 80 65 e0c6s32
3 e0c6s32 qfp14-80pin n pin description v dd v ss v s1 v l1 v l2 v l3 ca, cb osc1 osc2 osc3 osc4 k00?03, k10 p00?03, p10?13 r00?03 r10 r13 r11 r12 ampp ampm seg0?7 com0? reset test pin name i i o o o o i o i o i i/o o o o o o i i o o i i in/out power source (+) terminal power source (-) terminal oscillation and internal logic system regulated voltage output terminal lcd system regulated voltage output terminal (approx. -1.05 v) lcd system booster output terminal (v l1 x 2) lcd system booster output terminal (v l1 x 3) booster capacitor connecting terminal crystal oscillation input terminal crystal oscillation output terminal ceramic or cr oscillation input terminal (switchable by mask option, 6sa32 only) ceramic or cr oscillation output terminal (switchable by mask option, 6sa32 only) input terminal i/o terminal output terminal output terminal (dc or bz output may be selected by mask option) output terminal (dc or bz output may be selected by mask option) output terminal output terminal (dc or fout output may be selected by mask option) analog comparator non-inverted input terminal analog comparator inverted input terminal lcd segment output terminal (convertible to dc output by mask option) lcd common output terminal initial reset input terminal test input terminal qfp5-80pin 53 46 50 56 55 54 57, 58 52 51 49 48 25?9 30?7 38?1 44 45 43 42 23 24 1, 3?2, 64?0 60?3 47 2 qfp14-80pin 31 24 28 34 33 32 35, 36 30 29 27 26 3? 8?5 16?9 22 23 21 20 1 2 42?9, 61?0 38?1 25 60 pin no. function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ampp ampm k10 k03 k02 k01 k00 p03 p02 p01 p00 p13 p12 p11 p10 r03 r02 r01 r00 r12 no. pin name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 r11 r10 r13 v ss reset osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 n.c. cb ca com3 com2 com1 no. pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 com0 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 test n.c. = no connection no. pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 no. pin name 41 60 21 40 index 20 1 80 61 e0c6s32
4 e0c6s32 n electrical characteristics l absolute maximum ratings e0c6s32/6sa32/6sb32 rating supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time permissible dissipation * 2 * 1: * 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package (qfp5-80pin, qfp14-80pin). symbol v ss v i v iosc s i vss topr tstg tsol p d value -5.5 to 0.5 v ss - 0.3 to 0.5 v s1 - 0.3 to 0.5 10 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v ma c c mw (v dd =0v) rating supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time permissible dissipation * 2 * 1: * 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package (qfp5-80pin, qfp14-80pin). symbol v ss v i v iosc s i vss topr tstg tsol p d value -2.0 to 0.5 v ss - 0.3 to 0.5 v s1 - 0.3 to 0.5 10 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v ma c c mw (v dd =0v) l recommended operating conditions e0c6s32 e0c6sl32 condition supply voltage oscillation frequency symbol v ss f osc1 remark v dd =0v unit v khz (ta=-20 to 70 c) max. -1.8 typ. -3.0 32.768 min. -3.6 e0c6sl32 condition supply voltage oscillation frequency * 1: * 2: when switching to heavy load protection mode. note, however, that the on time for bls in the heavy load protection must be limi ted to 10 msec per second of operation time. the possibility of lcd panel display differs depending on the characteristics of the lcd panel. symbol v ss f osc1 remark v dd =0v v dd =0v, with software control * 1 v dd =0v, when the analog comparator is used unit v v v khz (ta=-20 to 70 c) max. -1.1 -0.9 * 2 -1.2 typ. -1.5 -1.5 -1.5 32.768 min. -1.8 -1.8 -1.8 e0c6sb32 condition supply voltage oscillation frequency * 1: * 2: when switching to heavy load protection mode. note, however, that the on time for bls in the heavy load protection must be limi ted to 10 msec per second of operation time. the possibility of lcd panel display differs depending on the characteristics of the lcd panel. symbol v ss f osc1 remark v dd =0v v dd =0v, with software control * 1 v dd =0v, when the analog comparator is used unit v v v khz (ta=-20 to 70 c) max. -1.1 -0.9 * 2 -1.2 typ. -1.5 -1.5 -1.5 32.768 min. -3.6 -3.6 -3.6 e0c6sa32 condition supply voltage oscillation frequency (1) oscillation frequency (2) symbol v ss f osc1 f osc3 remark v dd =0v duty 50 5% unit v khz khz (ta=-20 to 70 c) max. -1.8 1300 typ. -3.0 32.768 1000 min. -3.6 300
5 e0c6s32 l dc characteristics e0c6s32/6sa32 e0c6sl32/6sb32 unit v v v v a a a a ma ma ma ma a a a a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. 0 0 0.8? ss 0.9? ss 0.5 40 150 0 -1.8 -0.9 -3 -3 -200 typ. min. 0.2? ss 0.1? ss v ss v ss 0 4 25 -0.5 4.0 3.0 3 3 200 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v ih1 =0v, no pull down resistor v ih2 =0v, with pull down resistor v ih3 =0v, with pull down resistor v il =v ss v oh1 =0.1? ss v oh2 =0.1? ss v ol1 =0.9? ss v ol2 =0.9? ss v oh3 =-0.05v v ol3 =v l3 +0.05v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =0.1? ss v ol5 =0.9? ss condition k00?03, k10 p00?03, p10?13 reset, test k00?03, k10 p00?03, p10?13 reset, test k00?03, k10 p00?03, p10?13 ampp, ampm k00?03, k10 p00?03, p10?13 reset, test k00?03, k10 p00?03, p10?13 ampp, ampm reset, test r10, r11, r13 r00?03, r12 p00?03, p10?13 r10, r11, r13 r00?03, r12 p00?03, p10?13 com0?om3 seg0?eg37 seg0?eg37 unit v v v v a a a a a a a a a a a a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. 0 0 0.8? ss 0.9? ss 0.5 16 60 0 -300 -150 -3 -3 -100 typ. min. 0.2? ss 0.1? ss v ss v ss 0 2 9 -0.5 1,400 700 3 3 100 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v ih1 =0v, no pull down resistor v ih2 =0v, with pull down resistor v ih3 =0v, with pull down resistor v il =v ss v oh1 =0.1? ss v oh2 =0.1? ss v ol1 =0.9? ss v ol2 =0.9? ss v oh3 =-0.05v v ol3 =v l3 +0.05v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =0.1? ss v ol5 =0.9? ss condition k00?03, k10 p00?03, p10?13 reset, test k00?03, k10 p00?03, p10?13 reset, test k00?03, k10 p00?03, p10?13 ampp, ampm k00?03, k10 p00?03, p10?13 reset, test k00?03, k10 p00?03, p10?13 ampp, ampm reset, test r10, r11, r13 r00?03, r12 p00?03, p10?13 r10, r11, r13 r00?03, r12 p00?03, p10?13 com0?om3 seg0?eg37 seg0?eg37
6 e0c6s32 l analog circuit characteristics and current consumption e0c6s32 (normal mode) * 1: the svd circuit and analog comparator are in the off status. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.25 100 v dd -0.9 10 3 2.0 4.0 typ. -1.05 -2.40 0.65 2.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (ampp) inverted input (ampm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 1 without panel load * 1: the svd circuit is in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.25 100 v dd -0.9 10 3 34.0 40.0 typ. -1.05 -2.40 11.2 14.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (ampp) inverted input (ampm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 1 without panel load * 1: the svd circuit and analog comparator are in the off status. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -1.10 100 v dd -0.9 20 3 1.5 4.0 typ. -1.05 -1.20 0.65 2.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (ampp) inverted input (ampm) v ip =-1.1v, v im =v ip 30mv during halt during operation * 1 without panel load e0c6s32 (heavy load protection mode) e0c6sl32 (normal mode)
7 e0c6s32 * 1: the svd circuit is in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -1.10 100 v dd -0.9 20 3 34.0 40.0 typ. -1.05 -1.20 11.2 14.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (ampp) inverted input (ampm) v ip =-1.1v, v im =v ip 30mv during halt * 1 during operation * 1 without panel load e0c6sl32 (heavy load protection mode) e0c6sb32 (normal mode) * 1: the svd circuit and analog comparator are in the off status. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -1.10 100 v dd -0.9 20 3 1.5 4.0 typ. -1.05 -1.20 0.65 2.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (ampp) inverted input (ampm) v ip =-1.1v, v im =v ip 30mv during halt during operation * 1 without panel load e0c6sb32 (heavy load protection mode) * 1: the svd circuit is in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -1.10 100 v dd -0.9 20 3 34.0 40.0 typ. -1.05 -1.20 11.2 14.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (ampp) inverted input (ampm) v ip =-1.1v, v im =v ip 30mv during halt * 1 during operation * 1 without panel load
8 e0c6s32 e0c6sa32 (normal mode) * 1: the svd circuit and analog comparator are in the off status. unit v v v v s v mv ms a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.25 100 v dd -0.9 10 3 3.0 8.0 300 typ. -1.05 -2.40 1.5 4.0 150 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (ampp) inverted input (ampm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 1 during operation at 1mhz * 1 without panel load oscc="0" without panel load e0c6sa32 (heavy load protection mode) * 1: the svd circuit is in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. unit v v v v s v mv ms a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?5=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.25 100 v dd -0.9 10 3 110 120 330 typ. -1.05 -2.40 60 65 200 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t amp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (ampp) inverted input (ampm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 1 during operation at 1mhz * 1 without panel load oscc="0" without panel load l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. e0c6s32 (crystal oscillation circuit) unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.6 typ. 20 45 min. -1.8 -1.8 -10 35 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.8 to -3.6v c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss )
9 e0c6s32 e0c6sl32 (crystal oscillation circuit) * 1: items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. note, however, that the on time for bls must be limited to 10 msec per second of operation time. unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-1.5v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -1.8 typ. 20 45 min. -1.1 -1.1(-0.9) * 1 -10 35 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.1 to -1.8v (-0.9) * 1 c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c6sb32 (crystal oscillation circuit) * 1: items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. note, however, that the on time for bls must be limited to 10 msec per second of operation time. unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-1.5v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.6 typ. 20 45 min. -1.1 -1.1(-0.9) * 1 -10 35 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.1 to -3.6v (-0.9) * 1 c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c6sa32 (crystal oscillation circuit) unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.6 typ. 20 45 min. -1.8 -1.8 -10 35 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-2.2 to -3.6v c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c6sa32 (cr oscillation circuit) unit % v ms v (unless otherwise specified: v dd =0v, v ss =-3.0v, r cr =33k w , ta=25 c) max. 30 3 typ. 1mhz min. -30 -1.8 -1.8 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc3 vsta t sta vstp condition v ss =-2.2 to -3.6v (v ss ) (v ss ) e0c6sa32 (ceramic oscillation circuit) unit v ms v (unless otherwise specified: v dd =0v, v ss =-3.0v, ceramic oscillation: 1mhz, c gc =c dc =100pf, ta=25 c) max. 5 typ. min. -1.8 -1.8 characteristic oscillation start voltage oscillation start time oscillation stop voltage symbol vsta t sta vstp condition v ss =-2.2 to -3.6v (v ss ) (v ss )
10 e0c6s32 ?k00 ?k03 ?k10 ?p00 ?p03 ?p10 ?p13 ?ampm ?ampp ?r00 ?r03 ?cb ?ca ?v l1 ?v l2 ?v l3 ?v dd ?osc1 ?osc2 ?v s1 ?osc3 ?osc4 ?reset ?test ?v ss ?r12(fout) ?r11 ?r13(bz) ?r10(bz) e0c 6s32/6sl32/6sb32 ?seg0 ?seg37 ?com0 ?com3 i i/o o lamp piezo + x'tal c c1 gx cp c2 c3 c4 c5 n.c. n.c. 1.5 v (e0c6sl32/6sb32) or 3.0 v (e0c6s32) lcd panel ?cb ?ca ?v l1 ?v l2 ?v l3 ?v dd ?osc1 ?osc2 ?v s1 ?osc4 ?reset ?test ?v ss e0c6sa32 lamp piezo + x'tal c c1 3.0 v cr * 1 * 2 r cr c gc c dc ?osc3 gx cp c2 c3 c4 c5 * 1 ceramic oscillation * 2 cr oscillation lcd panel ?k00 ?k03 ?k10 ?p00 ?p03 ?p10 ?p13 ?ampm ?ampp ?r00 ?r03 ?r12(fout) ?r11 ?r13(bz) ?r10(bz) ?seg0 ?seg37 ?com0 ?com3 i i/o o x'tal c gx cr c gc c dc r cr c1~c5 cp crystal oscillator trimmer capacitor ceramic oscillator gate capacitance drain capacitance resistance for cr oscillation 32.768khz, ci(max.)=35k w 5~25pf 1mhz 100pf 100pf 33k w 0.1 f 3.3 f n basic external connection diagram note: the above table is simply an example, and is not guaranteed to work.
11 e0c6s32 20 0.1 25.6 0.4 41 64 14 0.1 19.6 0.4 25 40 index 0.35 0.1 24 1 80 65 2.7 0.1 0.26 3.4 max 2.8 1.5 0 12 0.15 0.05 0.8 12 0.1 14 0.4 41 60 12 0.1 14 0.4 21 40 index 0.18 20 1 80 61 1.4 0.1 0.1 1.7 max 1 0.5 0.2 0 10 0.125 0.5 +0.1 ?.05 +0.05 ?.025 unit: mm n package dimensions plastic qfp5-80pin plastic qfp14-80pin
e0c6s32 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110

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